By default, the tool derives the register name from the RTL signal name
and appends the _reg suffix. For example, if a signal is defined in
VHDL or Verilog, the elaborated instance name becomes wbDataForInputReg_reg:
- VHDL:
signal wbDataForInputReg : std_logic; - Verilog:
reg wbDataForInputReg;
The following figure shows the schematic of the register and its pins. It is possible to define a constraint on the register instance or pins.
Figure 1. Single-Bit Register in Elaborated Design
