Setting XDC File Scoping Properties Example - 2025.1 English - UG903

The following figure shows the uart_tx_i0 cell, an instance of the uart_tx module, which includes two hierarchical cells, uart_tx_ctl_i0 and uart_baud_gen_tx_i0.

The project includes an XDC file uart_tx_ctl.xdc to constrain the uart_tx_ctl module.

Figure 1. Setting XDC File Scoping Properties Example

Following are three equivalent Tcl examples to use the scoping properties on uart_tx_ctl.xdc. The same values can be set in the Properties windows of the XDC file in the Vivado IDE.

# Using the reference module name only:
set_property SCOPED_TO_REF uart_tx_ctl [get_files uart_tx_ctl.xdc]

# Using the cell name only:
set_property SCOPED_TO_CELLS uart_tx_i0/uart_tx_ctl_i0 [get_files uart_tx_ctl.xdc]

# Using both the uart_tx reference module and uart_tx_ctl_i0 instance: set_property SCOPED_TO_REF uart_tx [get_files uart_tx_ctl.xdc] set_property SCOPED_TO_CELLS uart_tx_ctl_i0 [get_files uart_tx_ctl.xdc]

When using Vivado Design Suite in Non-Project Mode, you can use the read_xdc command with the -ref and -cells options to achieve the same result:

# Using the reference module name only:
read_xdc -ref uart_tx_ctl uart_tx_ctl.xdc 

# Using the cell name only:
read_xdc -cells uart_tx_i0/uart_tx_ctl_i0 uart_tx_ctl.xdc

# Using both the uart_tx reference module and uart_tx_ctl_i0 instance:
read_xdc -ref uart_tx -cells uart_tx_ctl_i0 uart_tx_ctl.xdc

When a module is instantiated multiple times in the design, the module is uniquified during synthesis. After the synthesis, each instance of the RTL module points to a different module name. To apply some XDC constraints to all the instances of the original RTL module, the property ORIG_REF_NAME should be used instead of the property REF_NAME. For example:

set_property SCOPED_TO_REF [get_cells -hierarchical -filter {ORIG_REF_NAME == uart_tx_ctl}] [get_files uart_tx_ctl.xdc]
read_xdc -ref [get_cells -hierarchical -filter {ORIG_REF_NAME == uart_tx_ctl}] uart_tx_ctl.xdc