Setting XDC File Scoping Properties Example - Setting XDC File Scoping Properties Example - 2026.1 English - UG903

The following figure shows the uart_tx_i0 cell is an instance of the uart_tx module. It contains two hierarchical cells: uart_tx_ctl_i0 and uart_baud_gen_tx_i0. The project includes the uart_tx_ctl.xd file to constrain the uart_tx_ctl module.

Figure 1. Setting XDC File Scoping Properties Example

You can apply scoping properties to uart_tx_ctl.xdc in Tcl or through the XDC file's properties window in the Vivado IDE.

Use these Tcl commands in project mode to apply constraints using the following methods:

• Reference module name only:

  set_property SCOPED_TO_REF uart_tx_ctl [get_files uart_tx_ctl.xdc]
  

• Cell name only:

  set_property SCOPED_TO_CELLS uart_tx_i0/uart_tx_ctl_i0 [get_files uart_tx_ctl.xdc]
  

• Both the reference module and instance name:

  set_property SCOPED_TO_REF uart_tx [get_files uart_tx_ctl.xdc] 
  set_property SCOPED_TO_CELLS uart_tx_ctl_i0 [get_files uart_tx_ctl.xdc]
  

Use these Tcl commands in non-project mode to apply constraints using the following methods:

• Reference module name only:

  read_xdc -ref uart_tx_ctl uart_tx_ctl.xdc
  

• Cell name only:

  read_xdc -cells uart_tx_i0/uart_tx_ctl_i0 uart_tx_ctl.xdc
  

• Both the reference module and instance name:

  read_xdc -ref uart_tx -cells uart_tx_ctl_i0 uart_tx_ctl.xdc
  

When a module is instantiated multiple times, Vivado uniquifies the module during synthesis. After synthesis, each instance points to a different module name. To constrain all instances of the original RTL module, use the ORIG_REF_NAME property instead of REF_NAME.

When a module is instantiated multiple times in the design, the module is uniquified during synthesis. After synthesis, each instance of the RTL module points to a different module name. To apply XDC constraints to all instances of the original RTL module, use the ORIG_REF_NAME property instead of REF_NAME. Following is an example:

set_property SCOPED_TO_REF [get_cells -hierarchical -filter {ORIG_REF_NAME == uart_tx_ctl}] [get_files uart_tx_ctl.xdc]
read_xdc -ref [get_cells -hierarchical -filter {ORIG_REF_NAME == uart_tx_ctl}] uart_tx_ctl.xdc