To prevent negative effects on the top-level design, ensure timing constraints for an IP or sub‑module remain within its boundary. Clock definitions are the only exception in certain cases.
For example, defining a false‑path constraint in an IP XDC between two clocks that enter the IP is valid if asynchronous boundary circuitry exists in the IP. However, if the rest of the design lacks such circuitry and the clocks are related, the false path can break hardware functionality.
As explained in XDC Precedence, timing exceptions in the IP XDC override top‑level constraints due to higher precedence. This override is often undesired.
To avoid this, apply constraints only to netlist objects inside the IP. For a false path between two global clocks, constrain it from startpoint cells inside the IP to endpoint cells inside the IP. Use point‑to‑point exceptions instead of global exceptions.