When the Timing Constraints wizard is open, it prevents most actions in the Vivado IDE. This includes using the Tcl Console or running timing analysis to avoid database discrepancies. The wizard window stays in front of other Vivado IDE windows. To access Vivado IDE menus or windows, move the wizard window to the side.
Only the following features are available while the wizard is open:
- Reporting and visualizing the clock networks
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- Most wizard pages include buttons to generate and view the clock network report.
- The report shows clock topologies, their source points, and shared
segments for some clocks.
- Refer to Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for details.
- Searching a name in source files or an object in the design in memory
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- Use the Find and Find In Files dialog boxes from the Edit menu.
- These tools help retrieve design information while entering constraints in the wizard.
- Creating and viewing schematics
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- Select design objects in the main Vivado IDE window and visualize them in schematics.
- All schematics features are available.
- Only the last step of the wizard, Asynchronous Clock Domain Crossings, supports cross-probing from the Timing Paths tab.
- For details, refer to Vivado Design Suite User Guide: Using the Vivado IDE (UG893).
- Visualizing constraints in memory
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- Each wizard page includes a tab showing existing constraints of the same type recommended by that step.
- This view is useful for reviewing constraints already created in XDC files.
- The Timing Constraints window displays the full sequence of constraints in memory, organized by XDC file, including scoping information and invalid constraints.