You can rename generated clocks that are automatically created by the tool. This
is done by calling the create_generated_clock command with a limited
set of parameters:
create_generated_clock -name new_name [-source master_pin] [-master_clock master_clk] source_objectThe required arguments are the new clock name and the source object where the
auto-derived clock is created. This source object is typically the output pin of a clock
modifying block (CMB), a GT output pin in UltraScale
devices, or a similar source. Use the -source and
-master_clock options only when more than one clock
passes through the source pin, to remove ambiguity.
Important:
- If any of the following options are included:
-edges,-edge_shift,-divide_by,-multiply_by,-combinational,-duty_cycle, or-invert, the clock is not renamed. Instead, a new generated clock is created with the specified properties. - When a module such as IP, BD, and DFx is synthesized OOC, treat it as a
black box during top-level synthesis. In this case, internal pins and clock
names are no longer accessible. The top-level XDC constraints used for synthesis
cannot reference internal clock names or rename auto-derived clocks inside the
module.
- For OOC synthesis, top-level timing constraints must
reference OOC clocks through the module ports that propagate them. Use a
query such
as:
get_clocks -of_objects [get_pins <OOC_MODULE_OUTPUT_CLOCK_PORT>] - XDC constraints used for implementation do not have this limitation, because the full design is rebuilt before constraints are applied.
- For OOC synthesis, top-level timing constraints must
reference OOC clocks through the module ports that propagate them. Use a
query such
as: