Recommended Constraints Sequence - 2024.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2024-06-15
Version
2024.1 English

Whether you use one or several XDC files for your design, organize your constraints in the following sequence.

## Timing Assertions Section # Primary clocks
# Virtual clocks
# Generated clocks # Clock Groups
# Bus Skew constraints
# Input and output delay constraints

## Timing Exceptions Section # False Paths
# Max Delay / Min Delay # Multicycle Paths
# Case Analysis # Disable Timing

## Physical Constraints Section
# located anywhere in the file, preferably before or after the timing constraints # or stored in a separate constraint file
Note: The case analysis constraints that change the clock relationships or clock propagation should be defined prior to defining the generated clocks. This includes the case analysis defined on clock buffers that result in the output clock of the buffer to be impacted by the case analysis.

Start with the clock definitions. The clocks must be created before they can be used by any subsequent constraints. Any reference to a clock before it has been declared results in an error and the corresponding constraint is ignored. This is true within an individual constraint file, as well as across all the XDC files (or Tcl scripts) in your design.

The order of the constraint files matters. Be sure that the constraints in each file do not rely on the constraints of another file. If this is the case, read the file that contains the constraint dependencies last. If two constraint files have interdependencies, you must either merge them manually into one file that contains the proper sequence, or divide the files into several separate files and order them correctly.