Recommended Constraints Rules of IP/Sub-module XDC - Recommended Constraints Rules of IP/Sub-module XDC - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

Block-level constraints must follow these rules:

  • Avoid defining clocks in block‑level constraints if they are created at the top level. Use the following command to query them inside the block:
    set blockClock [get_clocks -of_objects [get_ports clkIn]]
  • Define a clock inside the block only if all of the following conditions are met:
    • The clock is on an input or inout port driving an instantiated input or inout buffer.
    • The clock exists on the output of a cell that creates or transforms a clock. Exceptions include MMCM, PLL, or special buffers automatically handled by timing tools.
    • Examples include the following:
      • Input clock with an input buffer
      • Clock divider
      • GT recovered clock
  • Specify input and output delay only if the port connects directly to a top-level port and the I/O buffer is inside the IP.
    • Examples include the following:
      • Input data ports with input buffers
      • Output data ports with output buffers
  • Avoid defining timing exceptions between clocks not bound to the IP.
  • Do not refer to clocks by name, as names can vary with top-level clocks or multiple instances.
  • Avoid placement constraints if the block can be instantiated multiple times in the same top-level design.