You must write RTL attributes in the RTL files. They typically control the mapping style of certain logic, preserve specific registers and nets, or manage design hierarchy in the final netlist. For more details, refer to the Synthesis Attributes section in the Vivado Design Suite User Guide: Synthesis (UG901).
Note: The
DONT_TOUCH attribute does not follow the properties of USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION. If DONT_TOUCH is
set in the synthesis XDC file, it propagates to implementation regardless of the USED_IN_IMPLEMENTATION value.For more
details on USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION, refer to Synthesis and Implementation Constraint Files.
Following is an example:
set_property DONT_TOUCH true [get_cells fsm_reg]