Treat period and waveform as the ideal characteristics
of a clock. As the clock enters the FPGA and propagates through the clock tree, the
edges incur delay and variations from noise and hardware behavior. You refer to these as
clock network latency and clock uncertainty.
Clock uncertainty includes:
- Clock jitter (refer to Clock Jitter)
- Phase error
- Any additional uncertainty that you have specified (refer to Additional Clock Uncertainty)
By default, the Vivado IDE treats clocks as non-ideal propagated clocks, so you get slack that includes insertion delay and uncertainty.