A primary clock comes from a board clock entering through an input port or a gigabit transceiver (GT) output pin, for example a recovered clock.
Note: Define primary clocks on GT outputs only
for 7 series devices. For AMD UltraScale™
, AMD UltraScale+™
, and AMD Versal™
devices, the timer automatically derives clocks on GT output ports.
Attach a primary clock to a netlist object. That object is the source point where clock edges originate and propagate downstream on the clock tree. Vivado IDE uses that source point as time zero when computing latency and uncertainty for the slack equation.
Important:
Vivado IDE
ignores all clock tree delays upstream of the point where you define the primary clock.
If you place it mid-tree, timing uses only part of its latency. Related clocks can then
report inaccurate skew and slack.
Define primary clocks first, because other timing constraints often reference them.