Primary Clocks Examples - Primary Clocks Examples - 2026.1 English - UG903

As shown in the figure, your board clock enters through port sysclk, then passes an input buffer and a clock buffer before reaching path registers.

• Period: 10 ns
• Duty cycle: 50%
• Phase: 0 ns

Figure 1. Primary Clock Example

create_clock -period 10 [get_ports sysclk]

Like sysclk, a board clock devclk enters the device through the port ClkIn.

• Period: 10 ns
• Duty cycle: 25%
• Phase shift: 90 degrees

Corresponding XDC:

create_clock -name devclk -period 10 -waveform {2.5 5} [get_ports ClkIn]

The following figure shows a transceiver gt0 recovers clock rxclk from a high-speed link. The clock rxclk has a 3.33 ns period and a 50% duty cycle. It routes to an MMCM, which generates several compensated clocks for the design.

When defining rxclk on the output driver pin of GT0, all the generated clocks driven by the MMCM have a common source point gt0/RXOUTCLK. The slack computation for paths between them uses the proper clock latency and uncertainty values.

create_clock -name rxclk -period 3.33 [get_pins gt0/RXOUTCLK]

Figure 2. GT Primary Clock Example

In the following figure, a differential buffer drives the PLL. In such a scenario, the primary clock must only be created on the positive input of the differential buffer. Creating a primary clock on each of the positive/negative inputs of the buffer would result in unrealistic CDC paths. For example:

create_clock -name sysclk -period 3.33 [get_ports SYS_CLK_clk_p]

Figure 3. Primary Clock on Differential Buffer Example