Placement Constraints - Placement Constraints - 2026.1 English - UG903

Apply placement constraints to cells to control locations within the device. The Vivado IDE supports many of the same placement constraints as the Integrated Software Environment (ISE) design suite and the plan ahead tool.

LUTNM

Apply a unique string name to two LUTs to control their placement on a single LUT site. Unlike HLUTNM, LUTNM can combine LUTs that belong to different hierarchical cells.

HLUTNM

Apply a unique string name to two LUTs in the same hierarchy to control their placement on a single LUT site. Use HLUTNM within a cell instantiated multiple times.

PROHIBIT

Prevent placement on a site.

PBLOCK

Attach to logical blocks to constrain them to a physical region in the device. Pblock is a read-only cell property that holds the name of the Pblock assigned to the cell. Change cell Pblock membership only by using XDC Tcl commands add_cells_to_pblock and remove_cells_from_pblock.

PACKAGE_PIN

Specify the location of a design port on a pin of the target device package.

LOC

Place a logical element from the netlist on a site in the device.

BEL

Place a logical element from the netlist on a specific BEL within a slice in the device.

For more information, refer to the following sections:

• XDC Precedence
• Defining Relatively Placed Macros