Placement Constraint Example One
Locate a block RAM at RAMB18_X0Y10 and fix its location.
% set_property LOC RAMB18_X0Y10 [get_cells u_ctrl0/ram0]Placement Constraint Example Two
Place a LUT in the C5LUT BEL position within a slice and fix its BEL assignment.
% set_property BEL C5LUT [get_cells u_ctrl0/lut0]Placement Constraint Example Three
Locate input bus registers in ILOGIC cells for shorter input delay.
% set_property IOB TRUE [get_cells mData_reg*]Placement Constraint Example Four
Combine two small LUTs into a single LUT6_2 that uses both O5 and O6 outputs.
% set_property LUTNM L0 [get_cells {u_ctrl0/dmux0 u_ctrl0/dmux1}]Placement Constraint Example Five
Prevent the placer from using the first column of block RAMs.
% set_property PROHIBIT TRUE [get_sites {RAMB18_X0Y* RAMB36_X0Y*}]Placement Constraint Example Six
Prevent the placer from using the clock region X0Y0.
% set_property PROHIBIT TRUE [get_sites -of [get_clock_regions X0Y0]]Placement Constraint Example Seven
Prevent the placer from using SLR0.
% set_property PROHIBIT TRUE [get_sites -of [get_slrs SLR0]]Important: When assigning both BEL and LOC properties
to a cell, BEL must be assigned before LOC.