Pin Assignment - Pin Assignment - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English
Use the following instructions to create or edit top-level port placement in the RTL Analysis, Synthesis, or Implementation views:
  1. Select the I/O Planning pre-configured layout.

  2. Open the windows shown in the following table:
    Table 1. Creating and Editing Existing Top-Level Ports Placement
    Window Function
    Device View and edit the location of the ports on the device floorplan.
    Package View and edit the location of the ports on the device package.
    I/O Ports Select a port, drag and drop it to a location in the Device or Package window, and review current assignment and properties.
    Package Pins View the resource utilization in each I/O bank.

For more information on Pin Assignment, refer to I/O Pin Planning in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).