Pin Assignment - 2024.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2024-06-15
Version
2024.1 English
To create and edit existing top-level ports placement when using the RTL Analysis, Synthesis, or Implementation views:
  1. Select the I/O Planning pre-configured layout.

  2. Open the windows shown in the following table:
    Table 1. Creating and Editing Existing Top-Level Ports Placement
    Window Function
    Device View and edit the location of the ports on the device floorplan.
    Package View and edit the location of the ports on the device package.
    I/O Ports Select a port, drag and drop it to a location on the Device or Package window, as well as review current assignment and properties of each port.
    Package Pins View the resource utilization in each I/O bank.

For more information on Pin Assignment, see the section 'IO Pin Planning' in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).