Output Delays - Output Delays - 2026.1 English - UG903

Similar to input delays, the Timing Constraints Wizard analyzes paths to output ports to identify source clocks and their active edges. Template selection rules match those in Input Delays step. The following figure shows several output constraints proposed by the wizard and partially edited by the user.

Figure 1. Recommended Output Delay Constraint Templates

For each constraint, you can edit three characteristics to specify the waveform that matches the actual interface timing on the board:

Synchronous

Describes the nature of the clock-data relationship (refer to Input Delays for more details).

Alignment

Describes the data transition alignment with respect to the active clock edge.

Setup/Hold

Use this when delay parameters are specified based on the data valid window timing outside the FPGA.

Skew (Source Synchronous only)

Use this when delay parameters are specified based on skew requirements on the FPGA output pin.

Data Rate and Edge

Describes the active clock edges constrained by the template (refer to Input Delays for more details).

As with recommended input delay constraints, the reference clock is usually the board clock, except in these cases:

• When there is a different board clock and output path internal clock periods. The wizard creates a virtual clock matching the internal clock waveform so setup analysis uses a one‑cycle path requirement.
• When the output path internal clock has a negative phase shift relative to the board clock.
  • The wizard creates a virtual clock matching the board clock waveform.
  • The wizard adds a multicycle path constraint to adjust setup analysis to one period plus the phase shift. This applies only to output ports that reference the virtual clock.
  Note: For positive phase shift, no virtual clock or multicycle constraint is required because setup defaults to one cycle minus the phase shift.
• When the forwarded clock identifies timing for the output path based on the shared clocking connectivity.
  • If a forwarded clock is found for the output path, it was created in step 3 of the wizard (refer to Forwarded Clocks). Otherwise, use the board clock or a virtual clock as the output delay reference.
  • Create the forwarded clock during the third step of the Forwarded Clocks wizard.
  • Otherwise, use the board clock or a virtual clock as the reference clock for the output delay constraint.

The following figure shows a basic example of an output source synchronous path along with its forwarded clock for the 7 series family. Both ODDR/OSERDES instances connect to the same clock net (highlighted in blue). The generated ck_vsf_clk_2 clock is already defined on the vsf_clk_2 output port.

Figure 2. Example of a Source Synchronous Output Path with its Forwarded Clock

The following figure shows the corresponding constraints in the wizard.

Figure 3. Recommended Source Synchronous Output Path Delay Constraint with a Forwarded Clock

After you select the proper template, enter the values for the delay parameters. To speed up the delay parameter entry task, select and edit several constraints with the same clock and template at once. After you apply the constraints, review their corresponding Tcl syntax in the Tcl Command Preview tab or click Next to continue the next step.