Use set_output_delay to specify the output path delay of
an output port relative to a clock edge at the design interface.
Video: For training on output delay,
refer to Vivado Design Suite QuickTake Video: Setting Output
Delay.
When you consider the application board, this delay represents the phase difference between the following:
- Data propagating from the FPGA output package pin, through the board, to another device.
- The relative reference board clock.
The output delay can be positive or negative, depending on the clock and data phase outside the FPGA.
Note: You can also set output delays on
internal data pins such as
STARTUPE3/DATA_OUT[0:3] (UltraScale+ devices).