Ordering Constraints for Better Runtime - Ordering Constraints for Better Runtime - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)
Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

When loading timing constraints into memory, the timing engine validates each new constraint and prints messages to flag potential issues. Some constraints partially invalidate the timing database, also known as the timing graph. Others require the timing database to be up-to-date to be properly applied. After the timing database is out of date, subsequent timing updates are needed, for example, to update auto-derivation clocks or to disable certain timing paths in the design.

XDC commands that query clocks or traverse the design to find netlist objects require an up‑to‑date timing database. Interleaving constraints and commands that affect the timing database state can increase runtime because the timing information gets repeatedly invalidated and updated.

To optimize runtime, AMD recommends ordering timing constraints and queries carefully. The following table groups XDC constraints by section. Keep these sections ordered when applying constraints from an XDC file or when opening a design with open_checkpoint to reduce constraint application time:
Table 1. XDC Constraints and their Impact on the Timing Graph
Section Command Comment
1
  • set_disable_timing
  • set_case_analysis
Disable timing and set static values:
  • Apply these first to prevent unnecessary analysis of disabled paths and values.
  • Keep this order within the section.
2
  • create_clock
  • create_generated_clock
  • set_clock_sense
Clock definitions:
  • Define clocks before using them in other constraints.
  • Generated clocks can be based on other generated clocks, so follow a define-before-use rule.
  • Keep this order within the section.
3
  • set_clock_latency
  • set_propagated_clock
  • set_clock_uncertainty
  • set_input_jitter
  • set_system_jitter
Clock properties:
  • These commands can trigger additional loading time, so group them together to minimize impact.
  • The order within this group does not matter
4
  • set_input_delay
  • set_output_delay
I/O delays:
  • Define I/O delays before timing exceptions.
  • These constraints have minimal impact on runtime, and order is flexible
  • The order within this group does not matter
5
  • set_clock_groups
  • set_false_path
  • set_min_delay
  • set_max_delay
  • set_multicycle_path
  • set_bus_skew
Timing exceptions:
  • These constraints define paths that are excluded or modified from standard timing analysis.
  • Apply them after clocks and I/O delays.
  • The order within this group does not matter
6
  • set_max_time_borrow
  • set_external_delay
Additional timing constraints:
  • These have little to no impact on constraint loading performance.
  • Apply them last.
  • The order within this group does not matter

Following the recommended order for timing constraints triggers a single timing update and minimizes runtime impact.

Some commands, such as all_fanin, all_fanout, all_clocks, and all_registers, have high intrinsic runtime and are best avoided:

  • all_fanin
  • all_fanout
  • all_clocks
  • all_registers

One of the most runtime-intensive combinations is using set_disable_timing with all_fanin or all_fanout. Avoid patterns like the following:

set_disable_timing –from <pin> -to [all_fanout …] 
set_disable_timing –from [all_fanin …] -to <pin>
Tip: When using the same query in multiple places, store the result in a Tcl variable and reuse it. This reduces redundant evaluations and improves runtime.

The following is an example of a non-optimal sequence:

create_clock –name clk1
create_generated_clock –name genclk1 –master_clock [get_clocks -of [get_pins ...]]
set_disable_timing ...
create_clock –name clk2
set_false_path -from [get_clocks -of [get_pins ff1/C]] 
set_case_analysis ...
create_clock –name clk3
set_max_delay -to [get_clocks -of [get_pins ff2/C]]

The following is an example of an improved, more runtime-efficient sequence:

set_disable_timing ... 
set_case_analysis ... 
create_clock –name clk1 create_clock –name clk2 
create_clock –name clk3
create_generated_clock –name genclk1 –master_clock [get_clocks -of [get_pins ...]] 
set_false_path -from [get_clocks -of [get_pins ff1/C]]
set_max_delay -to [get_clocks -of [get_pins ff2/C]]