Multicycles in Single Clock Domain - Multicycles in Single Clock Domain - 2026.1 English - UG903

Apply a multicycle constraint within one clock domain, or between clocks with identical waveforms. It behaves the same in both cases.

The static timing analysis (STA) tool resolves default setup and hold relationships.

The following are the setup and hold timing requirements:

• Setup check:
  T_{Datapath(max)} < TCLK_(t=Period) - T_Setup
• Hold check:
  T_{Datapath(min)} > TCLK_(t=0) + T_Hold