Multicycles in Single Clock Domain - 2024.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2024-06-15
Version
2024.1 English

A Multicycle constraint defined within the same clock domain or between two clocks with the same waveform (no phase-shift) works the same way. See the following figure.

Figure 1. Multicycle Constraint in Single Clock Domain

The default Setup and Hold relationships that are resolved by the Static Timing Analysis (STA) tool are shown in the following figure.

Figure 2. Default Setup and Hold Relationships

The Setup and Hold timing requirements are:

  • Setup check
    TDatapath(max) < TCLK(t=Period) - TSetup
  • Hold check
    TDatapath(min) > TCLK(t=0) + THold