Multicycles Between SLOW-to-FAST Clocks - Multicycles Between SLOW-to-FAST Clocks - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)
Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

In this scenario, use CLK1 as the slow launch clock and CLK2 as the fast capture clock.

Figure 1. Multicycles Between SLOW-to-FAST Clocks

For example, assume the following:

  • CLK2 is three times the frequency of CLK1.
  • A clock enable signal on the receiving registers lets you set a multicycle constraint between the clocks.
Figure 2. Multicycles Between SLOW-to-FAST Clocks

When no multicycle applies, STA resolves the default setup and hold relationships.

Figure 3. Default Setup and Hold Relationships