Multicycles Between FAST-to-SLOW Clocks - 2024.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2024-06-15
Version
2024.1 English

In the following scenario, the launch clock CLK1 is the fast clock and the capture clock CLK2 is the slow clock. See the following figure.

Figure 1. Multicycles Between FAST-to-SLOW Clocks

In the next example, the launch clock CLK1 is the fast clock. The capture clock CLK2 is the slow clock. Assume that CLK1 is three (3) times the frequency of CLK2. See the following figure.

Figure 2. Multicycles Between FAST-to-SLOW Clocks

The setup and hold relationships that are resolved by the STA tool when no multicycle is applied are shown in the following figure:

Figure 3. Default Setup and Hold Relationships