Use the multicycle path constraint to modify setup and hold relationships computed by the timer from the design’s clock waveforms. By default, the Vivado IDE timing engine performs single-cycle analysis. That analysis can be too restrictive and inappropriate for certain logic paths.
A common case is a logical path that needs more than one clock cycle for data to stabilize at the endpoint. If your startpoint and endpoint control logic allows it, use a multicycle path to relax the setup requirement.
The hold requirement can keep the original relationship, depending on your intent. This lets timing-driven algorithms focus on tighter paths and can also reduce runtime.