Multi-Bit Register Names - Multi-Bit Register Names - 2026.1 English - UG903

By default, Vivado names a multi-bit register based on the RTL signal name, followed by the _reg suffix. You can query and constrain only individual bits of the multi-bit register in your XDC commands.

For example, for the following signal definitions in VHDL and Verilog, the elaborated design generates the instance names loadState_reg[0], loadState_reg[1], and loadState_reg[2]:

• VHDL:

  signal loadState: std_logic_vector(2 downto 0);

• Verilog:

  reg [2:0] loadState;

Figure 1. Multi-Bit Register in Elaborated Design

The figure shows the register schematic. The multi-bit register appears as a vector of single-bit registers. The schematic displays the vector in a compact form when possible, but you can expand it to show each bit separately.

You can constrain each register individually or as a group by using these patterns:

• Register bit-0 only

  loadState_reg[0]

• All register bits

  loadState_reg[*]

Because these names match the post-synthesis netlist names, constraints based on them also work for implementation.