Logically exclusive clocks are defined on different source points but
share part of their clock tree through a multiplexer or other combinational logic. The
Timing Constraints
identifies these clocks and recommends a clock groups constraint when no timing paths
exist except through the shared clock tree. The following figure shows an example of two
clocks, clkA and clkB,
which are defined on different input ports and start overlapping on the output of a
BUFGMUX.
Figure 1. Example of Logically Exclusive Clocks with No Interaction
