LOCK_PINS - LOCK_PINS - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

Use LOCK_PINS, a cell property, to specify the mapping between logical LUT inputs (I0, I1, I2, …) and LUT physical input pins (A6, A5, A4, …). A common use is to force timing-critical LUT inputs to map to the fastest A6 and A5 physical LUT inputs.

LOCK_PINS Constraint Example One

Map I1 to A6 and I0 to A5 (swap the default mapping).

% set myLUT2	[get_cells u0/u1/i_365]
% set_property LOCK_PINS {I0:A5 I1:A6} $myLUT2
# Verify with:
% get_property LOCK_PINS $myLUT2

LOCK_PINS Constraint Example Two

Map I0 to A6 for a LUT6; mapping of I1 through I5 are don't-cares.

% set_property LOCK_PINS I0:A6 [get_cell u0/u1/i_768]