Input Delays - Input Delays - 2026.1 English - UG903

The Timing Constraints wizard analyzes paths from input ports to identify each destination clock and its active edges. Using that data, the Wizard recommends basic system‑synchronous input delay constraints based on Vivado IDE XDC templates (refer to XDC Templates for the templates). When you select a constraint entry in the Recommended Constraints table, the Waveform tab shows the waveform for the chosen template.

The following figure shows an example of several input constraints proposed by the wizard and partially edited by the user.

Figure 1. Recommended Input Delay Constraint Templates

For each constraint, edit three characteristics to specify the appropriate waveform that corresponds to the actual interface timing on the board:

• Synchronous: Describes the clock‑data relationship in your design.
  • System (for System Synchronous interface): Select this setting when data launches and captures on different clock edges separated by one or half a period.
  • Source (for Source Synchronous interface): Select this setting when data launches and captures on the same clock edge.
• Alignment: Describes data transition alignment with the active clock edge.
  • For System Synchronous interfaces only: Select Edge when clock and data transition simultaneously.
  • For Source Synchronous interfaces only, select the following options with the defined scenarios:
    • Select Center when the clock transitions in the middle of the data valid window.
    • Select Edge Direct when the clock transitions at the start of the data valid window.
    • Select Edge MMCM when the clock transitions at the end of the data valid window.
• Data Rate and Edge: Describes active clock edges constrained by the selected template. The wizard recommends a default value based on the active edges of the capturing sequential cell.

  Determine which clock edges launch data outside your FPGA. Select the appropriate setting:

  • Single Rise for rising edges only
  • Single Fall for falling edges only
  • Dual for both rising and falling edges

The recommended clock is typically the board clock associated with the input path’s sequential cell. If the internal clock comes from an MMCM or PLL generated clock, use the board clock driving that MMCM or PLL as the input constraint reference clock. Exceptions apply when the internal clock waveform differs from the board clock waveform, as in the scenarios shown.

Different period scenario

The input constraints tool automatically creates a virtual clock matching the internal clock waveform. This forces setup analysis to use a one‑cycle path requirement.

Positive phase-shift clock scenario

The wizard creates a virtual clock matching the board clock waveform. The wizard adds a multicycle path constraint between the virtual and internal clocks. This changes setup analysis to one period plus the phase shift. It simplifies constraints for input ports that reference the virtual clock.

Negative phase-shift clock scenario

In a negative phase‑shift clock scenario, no virtual clock or multicycle path constraint is required. Setup analysis naturally uses one cycle minus the phase shift.

The wizard does not let you change the selected reference clock for a constraint. Follow these steps to change it:

1. Manually edit the XDC files or use the Timing Constraints window after exiting the wizard.
2. Select the appropriate template.
3. Enter the delay parameter values in the Delay Parameters panel on the right side of the wizard.
   
   
4. Click Apply to validate the entries.
5. Review the input delay equations displayed below the delay fields and on some template waveforms.
6. To speed entry, select and edit several constraints that share the same clock and template.
7. After applying the constraints, review their Tcl syntax in the Tcl Command Preview tab.
8. Click Next to proceed to the next step.