Use set_input_delay to specify the input path delay on an
input port relative to a clock edge at the design interface.
Video: For training on input delay, refer to
Vivado Design Suite QuickTake Video: Setting Input
Delay.
On the application board, the input delay represents the phase difference between the following:
- Data propagating from an external chip through the board to an FPGA input package pin, and
- The relative reference board clock.
Therefore, the input delay can be positive or negative, depending on the clock and data phase at the device interface.
Note: You can also set input delays on
internal data pins such as
STARTUPE3/DATA_IN[0:3] (AMD UltraScale+™
devices).