I/O Constraints - I/O Constraints - 2026.1 English - UG903

I/O constraints configure the following:

• Ports
• Cells connected to ports

Typical constraints include the following:

• I/O standard
• I/O location

The Vivado Design Suite supports many of the same I/O constraints as the Integrated Software Environment (ISE) Design Suite.

The following list of I/O properties is not exhaustive. Properties apply to port objects unless otherwise stated.

DRIVE

Sets the output buffer drive strength (in mA), available with certain I/O standards only.

IOSTANDARD

Sets an I/O standard.

SLEW

Sets the slew rate (the rate of transition) behavior of a device output.

IN_TERM

Sets the configuration of the input termination resistance for an input port.

DIFF_TERM

Turns on or off the 100 ohm differential termination for primitives such as IBUFDS_DIFF_OUT.

KEEPER

Applies a weak driver on an tri-stateable output or bidirectional port to preserve its value when not being driven.

PULLTYPE

Applies a weak logic low or high level on a tri-stateable output or bidirectional port to prevent it from floating.

DCI_CASCADE

Defines a set of master and slave banks. The DCI reference voltage is chained from the master bank to the slaves. DCI_CASACDE is set on IOBANK objects.

INTERNAL_VREF

Frees the Vref pins of an I/O Bank and uses an internally generated Vref instead. INTERNAL_VREF is set on IOBANK objects

IODELAY_GROUP

Groups a set of IDELAY and IODELAY cells with an IDELAYCTRL to enable automatic replication and placement of IDELAYCTRL in a design.

IOB

Tells the placer to try to place FFs in I/O logic instead of the fabric slice. Assign this property to the register, not the port.

Important: Vivado and ISE handle IOB differently. Vivado allows IOB on both ports and registers, with register settings taking precedence in conflicts. It accepts only TRUE and FALSE, interpreting FORCE as TRUE and ignoring AUTO. Unlike ISE, if IOB TRUE cannot be honored, Vivado issues a critical warning instead of an error.

IOB_TRI_REG

For HDIO in AMD UltraScale+™ devices. Tells the placer to try to place FFs driving Tristate signals on HDIO bank IOBs in the I/O Logic instead of the fabric slice. Assign this property to the register, not the port.

For a complete list of I/O properties, details on port and cell properties, and coding examples, refer to Vivado Design Suite Properties Reference Guide (UG912). For details on applying these properties and related methodology, refer to the device SelectIO™ documents, such as 7 Series FPGAs SelectIO Resources User Guide (UG471).