Hierarchical Names - Hierarchical Names - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)
Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

Vivado synthesis flattens some or all design hierarchy levels unless synthesis is forced to keep the complete hierarchy. For more information, refer to the -flatten_hierarchy setting in the Vivado Design Suite User Guide: Synthesis (UG901).

Recommended: Use fully resolved hierarchical names in your synthesis constraints, with all hierarchical levels explicitly written using the / character. Avoid using implicit matching with the * character. Fully resolved names are more likely to match the final netlist regardless of hierarchy transformations.

For example, consider a register located in a sub-level of the design. In the elaborated design, the instance name appears as the following:

inst_A/inst_B/control_reg

During synthesis, you can get either a flat or hierarchical name depending on tool options or design structure.

  • Flat netlist instance name:
    inst_A/inst_B/control_reg (F)
  • Hierarchical netlist instance name:
    inst_A/inst_B/control_reg (H)

The / character is also used to mark flattened hierarchy levels, so the names can look the same. However, notice the difference when querying the object in memory:

These commands return the netlist object for F but not H:

get_cells -hierarchical *inst_B/control_reg
get_cells inst_A*control_reg

To avoid hierarchy-related issues:

  • Use get_* commands without the -hierarchical option.
  • Explicitly mark all hierarchy levels as they appear in the elaborated design with the / character.

Examples without -hierarchical:

  • Works for both flat and hierarchical netlists:
    get_cells inst_A/inst_B/*_reg
get_cells inst_*/inst_B/control_reg
  • Another option:
    get_cells -hier -filter {NAME =~ inst_A/inst_B/*_reg}
get_cells -hier -filter {NAME =~ inst_*/inst_B/control_reg}
CAUTION:
  • Avoid attaching constraints to hierarchical pins during synthesis because synthesis removes them like hierarchical cells.
  • Avoid constraining nets between combinational logic operators because synthesis often merges them into LUTs and removes them.
Recommended:
  • Regularly save your XDC files after editing.
  • Reload the elaborated design to ensure the constraints in memory match the constraints in the XDC files.
  • After running synthesis, load the synthesized design with the same synthesis XDC in memory, and run the timing summary report.

Some pre-synthesis constraints do not apply properly due to transformations during synthesis. To resolve these issues:

  1. Find the new XDC syntax that applies to the synthesized netlist.
  2. Save the constraints in a new XDC file for implementation only.
  3. Move synthesis-only constraints that no longer apply to a separate XDC file used exclusively for synthesis.