The Timing Constraints Wizard displays recommended constraints for generated clocks on a sequential cell output when the output drives clock pins of other sequential cells directly or through interconnect logic. User logic cannot multiply the master clock frequency, unlike PLL or MMCM. The wizard offers only a division coefficient option, as shown in the figure.
Figure 1.
Generated
Clocks Page of the Timing Constraints Wizard
If multiple master clocks reach a generated clock source point, the wizard creates generated clocks with unique names and references to each master clock.
The figure shows clk3 and clk4 reaching the sequential cell FDIV_reg. In this situation, the wizard recommends two generated clock
constraints: FDIV and FDIV_1.
Tip: Certain clocking topologies, such as
cascaded registers on the clock path, require you to run the Timing Constraints Wizard multiple times to
discover all the missing generated clocks.