Forwarded Clocks - Forwarded Clocks - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)
Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

The Timing Constraints Wizard recommends generated clock constraints on output ports driven by double data‑rate registers with constant inputs. The wizard adjusts the clock phase according to constant input connectivity: positive (0°) or inverted (180°). The constraint references the master clock reaching the double data‑rate register’s clock pin. Refer to the Source Clock column in the Recommended Constraints table in the following figure.

Figure 1. Recommended Forwarded Clocks

For the 7 series device family, the wizard recognizes the topology shown in the following figure. The master clock type and output buffer type have no restrictions for this topology.

Figure 2. 7 Series Forwarded Clock Typical Circuitry

For the UltraScale device family, ODDR and ODDRE1 primitives automatically retarget to OSERDESE3 with property ODDR_MODE=TRUE. The wizard recognizes the topology where OSERDESE3/D[0] connects to 1 and OSERDESE3/D[4] connects to 0, resulting in no phase shift.

Figure 3. UltraScale Forwarded Clock Typical Circuitry