Fixed Routing - Fixed Routing - 2026.1 English - UG903

Fixed routing lets you lock down the routing of a net, similar to directed routing in ISE. To lock routing, use the three net properties:

Before fixing a net’s routing, make sure all cells connected to that net are already placed. Fixed routing cannot be guaranteed unless all associated cells are fixed first. Here’s an example of how to fully fix the routing of a net, using netA (selected in blue) as shown in the figure.

You can query the routing information of any net after you load the implemented design in memory:

% set net [get_nets netA]
% get_property ROUTE $net
{ CLBLL_LL_CQ CLBLL_LOGIC_OUTS6 FAN_ALT5 FAN_BOUNCE5 { IMUX_L17 CLBLL_LL_B3 } IMUX_L11 CLBLL_LL_A4 }

The routing appears as a sequence of relative routing node names. Fanout is shown using embedded curly braces. To fix the routing, set the following property on the net:

% set_property IS_ROUTE_FIXED TRUE $net

To back-annotate constraints in your XDC file for future runs, also preserve placement of all cells connected to the fixed net. Check this by selecting the cells in the schematics or device view and reviewing their LOC and BEL property values in the Properties window. Or, query them directly from the Tcl Console:

% get_property LOC [get_cells {a0 L0 L1}] SLICE_X0Y47 SLICE_X0Y47 SLICE_X0Y47
% get_property BEL [get_cells {a0 L0 L1}] SLICEL.CFF SLICEL.A6LUT SLICEL.B6LUT

Because fixed routes are often timing-critical, you must also capture the LUT pin mappings in the LOCK_PINS property of the LUT. This prevents the router from swapping the pins.

You can query the site pin of each logical pin from the Tcl Console:

% get_site_pins -of [get_pins {L0/I1 L0/I0}] SLICE_X0Y47/A4 SLICE_X0Y47/A2
% get_site_pins -of [get_pins {L1/I1 L1/I0}] SLICE_X0Y47/B3 SLICE_X0Y47/B2

The complete XDC constraints required to fix the routing of net netA are:

set_property BEL CFF [get_cells a0] 
set_property BEL A6LUT [get_cells L0] 
set_property BEL B6LUT [get_cells L1]
set_property LOC SLICE_X0Y47 [get_cells {a0 L0 L1}] 
set_property LOCK_PINS {I1:A4 I0:A2} [get_cells L0] 
set_property LOCK_PINS {I1:A3 I0:A2} [get_cells L1]
set_property FIXED_ROUTE { CLBLL_LL_CQ CLBLL_LOGIC_OUTS6 FAN_ALT5 FAN_BOUNCE5	{
IMUX_L17 CLBLL_LL_B3 } IMUX_L11 CLBLL_LL_A4 } [get_nets netA]

If you are using interactive Tcl commands instead of XDC, specify several placement constraints in a single command using place_cell:

place_cell a0 SLICE_X0Y47/CFF L0 SLICE_X0Y47/A6LUT L1 SLICE_X0Y47/B6LUT

For more information on place_cell, refer to the Vivado Design Suite Tcl Command Reference Guide (UG835).