Fixed Routing - 2024.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2024-06-15
Version
2024.1 English

Fixed Routing is the mechanism for locking down routing, similar to Directed Routing in ISE. Locking down a net routing resources involves three net properties. See the following table.

Table 1. Net Properties
Property Function
ROUTE Read-only net property
IS_ROUTE_FIXED Flag to mark the whole route as fixed
FIXED_ROUTE The fixed-route portion of a net

To guarantee that a net routing can be fixed, all of its cells must also be fixed in advance.

Following is an example of a fully-fixed route. The example takes the design in the following figure and creates the constraints to fix the routing of the net netA (selected in blue).

Figure 1. Simple Design to Illustrate Routing Constraints

You can query the routing information of any net after loading the implemented design in memory:

% set net [get_nets netA]
% get_property ROUTE $net
{ CLBLL_LL_CQ CLBLL_LOGIC_OUTS6 FAN_ALT5 FAN_BOUNCE5 { IMUX_L17 CLBLL_LL_B3 } IMUX_L11 CLBLL_LL_A4 }

The routing is defined as a series of relative routing node names with fanout denoted using embedded curly braces. The routing is fixed by setting the following property on the net:

% set_property IS_ROUTE_FIXED TRUE $net

To back-annotate the constraints in your XDC file for future runs, the placement of all the cells connected to the fixed net must also be preserved. You can query this information by selecting the cells in the schematics or device view, and look at their LOC/BEL property values in the Properties window. Or, you can query those values directly from the Tcl Console:

% get_property LOC [get_cells {a0 L0 L1}] SLICE_X0Y47 SLICE_X0Y47 SLICE_X0Y47
% get_property BEL [get_cells {a0 L0 L1}] SLICEL.CFF SLICEL.A6LUT SLICEL.B6LUT

Because fixed routes are often timing-critical, LUT pins mapping must also be captured in the LOCK_PINS property of the LUT to prevent the router from swapping pins.

Again, you can query the site pin of each logical pin from the Tcl Console:

% get_site_pins -of [get_pins {L0/I1 L0/I0}] SLICE_X0Y47/A4 SLICE_X0Y47/A2
% get_site_pins -of [get_pins {L1/I1 L1/I0}] SLICE_X0Y47/B3 SLICE_X0Y47/B2

The complete XDC constraints required to fix the routing of net netA are:

set_property BEL CFF [get_cells a0] set_property BEL A6LUT [get_cells L0] set_property BEL B6LUT [get_cells L1]
set_property LOC SLICE_X0Y47 [get_cells {a0 L0 L1}] set_property LOCK_PINS {I1:A4 I0:A2} [get_cells L0] set_property LOCK_PINS {I1:A3 I0:A2} [get_cells L1]
set_property FIXED_ROUTE { CLBLL_LL_CQ CLBLL_LOGIC_OUTS6 FAN_ALT5 FAN_BOUNCE5	{
IMUX_L17 CLBLL_LL_B3 }	IMUX_L11 CLBLL_LL_A4 } [get_nets netA]

If you are using interactive Tcl commands instead of XDC, several placement constraints can be specified at once with the place_cell command, as shown below:

place_cell a0 SLICE_X0Y47/CFF L0 SLICE_X0Y47/A6LUT L1 SLICE_X0Y47/B6LUT

For more information on place_cell, see the Vivado Design Suite Tcl Command Reference Guide (UG835).