The Timing Constraints Wizard analyzes the feedback loop connectivity of the
MMCM and PLL cells in the design. Apply min/max external delay constraints when CLKFBIN and CLKFBOUT
connect to design ports through IO buffers and COMPENSATION=EXTERNAL is set. Refer to the following figure for
recommended values.
The following figure shows a typical MMCM circuit with an external feedback path.
The Timing Constraints Wizard can omit recommending external delay constraints if a sequential cell in the feedback path generates a forwarded clock. In that case, create the constraints manually or in the Timing Constraints window after the wizard closes. The ODDR primitive is an exception because it is supported for forwarded clocks.