Your design can include several operation modes that require different clocks. You usually select between clocks with a multiplexer, such as BUFGMUX or BUFGCTRL, or a LUT.
Recommended: Avoid using LUTs in clock
trees whenever possible.
Because these cells are combinational, the Vivado IDE propagates all incoming clocks to the output. In Vivado IDE, several timing clocks can exist on a clock tree at the same time. This helps report all operation modes together, but hardware cannot do this.
Call such clocks exclusive clocks. Constrain them with set_clock_groups:
-
-logically_exclusive -
-physically_exclusive