Exclusive Clock Groups Example - Exclusive Clock Groups Example - 2026.1 English - UG903

An MMCM generates clk0 and clk1, and you connect them to the BUFGMUX instance clkmux. The clkmux output drives the design clock tree.

By default, Vivado IDE analyzes paths between clk0 and clk1, even though both clocks share the same tree and never exist at the same time.

set_clock_groups -name exclusive_clk0_clk1 -physically_exclusive \
-group clk0 -group clk1

The following options are equivalent in AMD FPGAs:

• -logically_exclusive
• -physically_exclusive

These labels come from ASIC crosstalk analysis modes, which you do not need to distinguish for AMD FPGAs.