Exclusive Clock Groups Example - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

An MMCM instance generates clk0 and clk1 which are connected to the BUFGMUX instance clkmux. The output of clkmux drives the design clock tree.

By default, the Vivado IDE analyzes paths between clk0 and clk1 even though both clocks share the same clock tree and cannot exist at the same time.

You must enter the following constraint to disable the analysis between the two clocks:

set_clock_groups -name exclusive_clk0_clk1 -physically_exclusive \
-group clk0 -group clk1

The following options are equivalent in the context of AMD FPGAs:

  • -logically_exclusive
  • -physically_exclusive

The physically and logically labels refer to various signal integrity analysis (crosstalk) modes in ASIC technologies which is not needed for AMD FPGAs.