If constraints overlap (for example, if several timing exceptions are applied to the same path), the priority from highest to lowest is the following:
- Clock groups (
set_clock_groups) - False path (
set_false_path) - Maximum delay path (
set_max_delay) and Minimum Delay Path (set_min_delay) - Multicycle paths (
set_multicycle_path)
Note: The
set_bus_skew constraint
does not affect the precedence of the constraints listed above. It does not override,
and is not overridden by, clock groups, max delays, false paths, or multicycle paths.
This is because bus skew is not a constraint on a particular path, but a constraint
between paths.Note: You can use the
-reset_path
option to alter the priority between false path, maximum or minimum delay, and
multicycle path constraints. The clock group constraint cannot be overridden. A maximum
or minimum delay or a multicycle path constraint can override a previously defined false
path or maximum or minimum delay constraint only if both constraints use the exact same
-from, -to, and -through
arguments, and the newer constraint includes the -reset_path
option.For the same type of timing exception, the more specific the constraint, the higher its precedence. You can control a constraint’s specificity by adjusting the filtering options and choosing the appropriate types of objects.
The priority of objects used in timing exceptions follows these rules:
- Ports, pins, and cells have higher precedence than clocks. If you use both a cell and one of its pins, the tool prioritizes the pin.
- Clocks always have lower priority. A timing exception that references clock objects has lower precedence than one using ports, pins, or cells.
The precedence rule for the filters, from highest to lowest precedence is as follows:
-
-from,-through,-to -
-from,-to -
-from,-through -
-from -
-through,-to -
-to -
-through
Important: Cells used in either the
-from or -to options always have higher precedence
than a clock, even if the clock is used in a more specific case such as
-from, -through, -to.