Example Three: Duty Cycle Change and Phase Shift with -edges and -edge_shift Options - Example Three: Duty Cycle Change and Phase Shift with -edges and -edge_shift Options - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

Shift each generated clock edge individually with -edge_shift. Use it only when you need a phase shift. You cannot combine -edge_shift with -divide_by, -multiply_by, or -invert.

Assume master clock clkin has a 10 ns period and a 50% duty cycle. It reaches cell mmcm0, which generates a clock with a 25% duty cycle, shifted by 90 degrees. Reference master clock edges 1, 2, and 3 at 0 ns, 5 ns, and 10 ns. Shift the first and third edges by 2.5 ns to get the target waveform.

create_clock -name clkin -period 10 [get_ports clkin]
create_generated_clock -name 
clkshift -source [get_pins
mmcm0/CLKIN] \ 
 -edges {1 2 3} -edge_shift {2.5 0
2.5} [get_pins mmcm0/CLKOUT] 
# First rising edge:	0ns + 2.5ns = 2.5ns
# Falling edge:	5ns + 0ns	= 5ns
# Second rising edge: 10ns + 2.5ns = 12.5ns
Note: -edge_shift values can be positive or negative.
Figure 1. Generated Clock Example Three