Example One: Simple Division by 2 - Example One: Simple Division by 2 - 2026.1 English - UG903

The primary clock clkin has a period of 10 ns. Divide it by 2 using register REGA, which drives other registers' clock pins. Name the generated clock clkdiv2.

Use either of the two equivalent constraints:

create_clock -name 
clkin -period 10 [get_ports clkin]

# Option 1: master clock source is the primary clock source point
create_generated_clock -name clkdiv2 \
      -source [get_ports clkin] \
      -divide_by 2 [get_pins REGA/Q]

# Option 2: master clock source is the REGA clock pin
create_generated_clock -name clkdiv2 \
      -source [get_pins REGA/C] \
      -divide_by 2 [get_pins REGA/Q]