The primary clock clkin
has a period of 10 ns.
It is divided by 2 by the register REGA which drives other registers clock pin. The
corresponding generated clock is called clkdiv2
.
Two equivalent constraints are provided below:
create_clock -name clkin -period 10 [get_ports clkin]
# Option 1: master clock source is the primary clock source point create_generated_clock -name clkdiv2 -source [get_ports clkin] -divide_by 2 \
[get_pins REGA/Q]
# Option 2: master clock source is the REGA clock pin
create_generated_clock -name clkdiv2 -source [get_pins REGA/C] -divide_by 2 \ [get_pins REGA/Q]
Figure 1. Generated Clock Example One