You can specify -divide_by and -multiply_by at the
same time in the Vivado IDE.
This extends Synopsys design constraints (SDC) support. You can manually define clocks from MMCM or PLL instances, though the engine can create them automatically.
Refer to Automatically Derived Clocks for more information.
Consider cell mmcm0 from Example Three: Duty Cycle Change and Phase Shift with -edges and -edge_shift Options. Assume it multiplies the master
clock frequency by 4/3. Use this generated clock definition:
create_generated_clock -name clk43 -source [get_pins mmcm0/CLKIN] -multiply_by 4 \
-divide_by 3 [get_pins mmcm0/CLKOUT]
When you constrain an MMCM or PLL output, verify the generated clock waveform matches the MMCM or PLL configuration.