Assume your master clock drives a divide-by-2 register and a clock multiplexer that selects either the master clock or the divided-by-2 clock. Two paths exist from the master clock to the generated clock: one through a sequential arc and one through a combinational arc. Create a generated clock on the multiplexer output that reflects the latency of the combinational path.
Use the -combinational option:
create_generated_clock -name clkout -source [get_pins mmcm0/CLKIN] -combinational [get_pins MUX/O]