Example: Build an RLOC List for the Example Circuit - Example: Build an RLOC List for the Example Circuit - 2026.1 English

Example: Build an RLOC List for the Example Circuit - Example: Build an RLOC List for the Example Circuit - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID

UG903

Release Date

2026-07-01

Version

2026.1 English

# create macro cell list: input register stage and BRAM cells
set cells [get_cells -hier	[list ireg0* ireg1* *SIMPLE_PRIM36.ram]] create_macro m0
update_macro m0 -absolute_grid [buildRLOCList $cells]

To see the dictionary list created by buildRLOCList:

$ puts [buildRLOCList $cells]
{ireg0[6]} X2Y10 {ireg0[5]} X2Y11 {ireg0[4]} X2Y6 {ireg0[3]} X2Y7 . . .

When your design includes many macro cells or cells buried in hierarchy, specifying an explicit list of cell-RLOC pairs becomes complex and error-prone. Use Tcl automation to simplify creation and management of XDC macros.