Elaborated Design Constraints - Elaborated Design Constraints - 2026.1 English - UG903

At this stage, net delay modeling is not highly accurate. The main goal is to obtain a synthesized netlist that meets timing or fails by only a small margin before starting implementation. Reaching this point often requires multiple iterations of XDC and RTL modifications.

The RTL-based XDC creation process uses the elaborated design to find object names that require synthesis constraints.

Use the Tcl Console to validate the syntax of XDC commands before saving them to XDC files. In the elaborated design, you can create constraints, query clocks, and query design objects. However, you cannot run any timing report commands.

Figure 1. Creating Constraints with the Elaborated Design

When writing constraints for synthesis, the following design objects are safe to use:

• Top-level ports
• Manually instantiated primitives, including cells and pins

Some RTL names change or disappear during the creation of the elaborated design. Following are the most common cases:

• Single-Bit Register Names
• Multi-Bit Register Names
• Absorbed Registers and Nets
• Hierarchical Names