Define sets of design elements with U Set (U_SET) or HU Set (HU_SET) constraints.
- Place each element of the set in relation to the other elements by using relative location (RLOC) constraints.
- Associate logic elements with RLOC constraints and common set names in a relationally placed macro (RPM).
U_SET, HU_SET, and RLOC constraints:
- Define them as properties in the HDL design files.
- Are not supported in Xilinx design constraints (XDC).
Tip: Use the
create_macro and update_macro commands in
the AMD Vivado™ Design Suite to define macro objects that
act like RPMs within the design. Refer to XDC Macros for more details.For more information on U_SET, HU_SET, and RLOC constraints, refer to Vivado Design Suite Properties Reference Guide (UG912).