Dedicated Hardware Resources - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

The dedicated hardware resources of AMD FPGAs efficiently support a large number of design clocks. These clocks are usually generated by an external component on the board. They usually enter the device through an input port.

They can also be generated by special primitives called Clock Modifying Blocks, such as:

  • MMCM
  • PLL
  • BUFR

They can also be transformed by regular cells such as LUTs and registers.

The following sections describe how to best define clocks based on where they originate.