Creating Synthesis Constraints - 2024.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2024-06-15
Version
2024.1 English

The Vivado Synthesis transforms the RTL description of your design into a technology mapped netlist. This process happens in several steps, and includes a number of timing-driven optimizations.

AMD FPGAs include many logic features that can be used in many different ways. Your constraints are needed to guide the synthesis engine towards a solution that meets all the design requirements at the end of implementation.

There are four categories of constraints for the Vivado IDE synthesis: